# 68000 Conditions Code Register

## 68000 Conditions Code Register

### 68000 Conditions Code Register

68000 Conditions and the Condition Code Register

The computational power of all computers lies in their ability to choose between two or more courses of actions on the basis of the available information. Without such powers of decision, the computer would be almost entirely worthless, as it could only execute a long list of instructions “blindly”.
Instructions that make decisions at the assembly language level are used to implement constructs like IF…THEN…ELSE and REPEAT…UNTIL at the high-level language level. We are now going to look at the family of instructions that enable the programmer to synthesise high-level control constructs.

Learning Outcomes:
On completion of this lecture, you will be able to:

• Discuss the need for conditional instructions;
• Describe the flag bits of the Condition Code register;
• Discuss the conditions the 68000 recognises;
• Implement compare, test and bit manipulation instructions;
• Implement conditional branches.

9.1      68000 conditions

There are instructions that only have an effect if a particular condition holds true. In the 68000, conditions are:

• Boolean expressions that take the five bits of the Condition Code Register (Fig. 10.1)
• True, false
• the Boolean operators ‘and’ ,‘or’, ‘eor’ and ‘not’.

Fig. 9.1 Conditions the 68000 recognises

A computer chooses between two courses of action by examining the state of one or more bits in its CCR and associating one action with the outcome of the test and another action with the other outcome.

• Calculating Condition in the CCR

Remember that the Condition Code register (CCR) is a special register of the CPU. It contains a set of flag bits (X, N, Z, V and C) which are set or clear according to the result of an arithmetic or logical operation. That is, the CCR provides a status report about the operation.
Many instructions have an effect on the X, N, Z, V and C bits of the CCR. In the Instruction Set Summary:
* means the bit is affected ‘as you might expect’ --
– means the bit is unaffected -- it retains its present value

What you might expect…

• C: the carry/borrow bit. Set if arithmetic carry or borrow; cleared otherwise.
• V: the arithmetic overflow bit. Set if sign overflow occurred; cleared otherwise.
• Z: the zero bit. Set if the result is zero; cleared otherwise.
• N: the negative bit. Set if the result is negative; cleared otherwise.
• X: the extend bit. This is the same as the carry bit, but is only affected by a subset of the instructions that affect the carry bit: the ‘arithmetic’ instructions. X is set if arithmetic carry or borrow has occurred.

Some instructions have no effect apart from their effect on the CCR: TST, CMP, BTST, etc…
The purpose of these instructions is to calculate an appropriate condition and place it in the CCR so that it can have a desired effect on program execution.

• Compare and test Instructions: CMP and TST

• CMP -- the Compare Instruction sets the CCR as if the first operand had been subtracted from the second. The N-, Z-, V-, and C-bits are all updated and the X-bit remains unaffected. The destination operand must be a data register and the source operand may be specified by any of the 68000’s addressing modes.

e.g.:
CMP.L D0,D1          evaluates [D1(0:31)] – [D0(0:31)]
CMP.B TEMP1,D3     evaluates [D3(0:7)] – [(TEMP1)]
CMP.L TEMP1,D3      evaluates [D3(0:31)] – [(TEMP1)]
CMP.W (A3),D2        evaluates [D2(0:15)] – [M([A3))]

• TST -- the Test [against zero] Instruction reads the operand, compares it with zero, and sets the bits of the CCR accordingly. For example, TST D3 has a similar effect to CMP #0,D3.

• Bit manipulation instructions: BTST, BSET, BCLR, BCHG

The 68000 provides a family of four instructions that act on a single bit of an operand, rather than the entire operand: BTST, BSET, BCLR, BCHG. The selected bit is first tested to determine whether it is a one or a zero, and then it is operated on according to the actual instruction. In each of the bit manipulation instructions, the complement of the selected bit is moved to the Z-bit of the CCR and then the bit is left unchanged, set, cleared or complemented. The N-,V-,C- and X-bits are not affected.

• BTST: Bit TeST tests a bit of an operand. If the test bit is zero, the Z-bit of the CCR is set, else the Z-bit is cleared. A bit test does not affect the value of the operand under test in any way. The location of the bit to be tested is specified by a constant, or as the contents of a data register. For example, BTST #3,(A0) tests bit 3 of the byte in memory pointed at by A0. BTST D0,(A0) tests the bit in the byte pointed at by A0 whose bit-number is in D0.
• BSET: Bit Test and SET causes the Z-bit of the CCR to be set if the specified bit of an operand is zero, and then forces it to be set to one. eg: BTSET #4,D0.
• BCLR: Bit and CLeaR works exactly like BSET, except that the specified bit is cleared after it has been tested.
• BCHG: Bit test and CHanGe causes the value of the specified bit to be tested and then inverts its state.

9.5      Branch Conditionally

The 68000 provides the programmer with a toolkit containing instructions for the implementation of conditional structures:
Bcc     <label>         Branch to label on condition cc true.
The condition cc, calculated into the CCR, is any one of the fourteen conditions listed below:

Fig. 9.2 authorised conditions with the Bcc instruction

After an arithmetic or logical operation is carried out, the value of the Z, N, C, V flags in the CCR are updated accordingly. These flag bits are used to determine whether the appropriate logical condition is true or false. For example, BCS LABEL causes the state of the carry-bit to be tested. If it is set, a branch is made to the point in the program called LABEL. Otherwise, the instruction immediately following BCS LABEL is executed.
We can divide branch instructions into two classes: those that branch on an unsigned condition and those that branch on a signed condition. Branch instructions used in conjunction with signed arithmetic are: BGE (Branch on Greater than or Equal), BGT (Branch on Greater than), BLE (Branch on Less than or Equal), and BLT (Branch on Less than). Branch instructions used in conjunction with unsigned arithmetic are: BHI (Branch on Higher than), BCC (Branch on Carry Clear), BLS (Branch on Less than or same), and BCS (Branch on Carry Set). Some assemblers let you write BHS (Branch on Higher or Same) instead of BCC, and BLO (Branch on Lower or Same) rather than BCS.

E.g: if [D0]=\$CO and we perform the operation CMP.B #\$2,D0, the result is C016-2516=9B16, and Z=0, N=1, V=0, C=0. If we perform a BHS, the branch will be taken because \$CO is higher than \$25 when using unsigned arithmetic. If we use a signed branch, BGE, the branch will not be taken, because \$CO is less than \$25 (i.e., -64 is less than 37).
9.6      Test Condition, Decrement and Branch Conditionally

The DBcc instruction makes it easier to execute a loop a given number of times. The assembly language form is:
DBcc   Dn,<label>    test condition cc, decrement Dn and branch to label if cc is false
Dn is a data register and <label> is a label used to specify a branch address. The label is assembled to a 16-bit signed displacement which permits a range of 32K bytes.
If the result of the test is true, the branch is not taken and the next instruction in sequence is executed (i.e., exit the loop).
If the specified condition is not true, the low-order 16-bits of register Dn are decremented by 1. In addition, if the resulting contents of Dn are equal to -1, the next instruction in sequence is executed.
Note that DBcc has the opposite effect to a Bcc instruction; a Bcc instruction takes the branch on condition cc true, whereas a DBcc instruction exits the branch on condition cc true.
As in the case of of the Bcc instruction, there are 14 possible computed values of condition cc, plus two static values: cc=T (true) and cc=F (false), as shown in Fig.10.1.
e.g.: DBF Dn,<label>  always causes Dn to be decremented and a branch made to <label> until the contents of Dn are -1. Many assemblers permit the use of the mnemonic DBRA instead of DBF.

• Conclusion
• CMP is exactly like a SUB instruction, except that it doesn’t replace the second operand with the result.
• TST is somewhat equivalent to CMP #0,…
• The bit test family of instruction is used mostly when dealing with peripherals. Memory being byte addressable, if the destination address is a memory location, the source operand is treated as a modulo-8 value. If the destination address is a data register, then the source operand is treated as a modulo-32 value.
• Bcc and DBcc are conditional branch instructions. The DBcc instruction is designed to support applications in which one of two conditions may terminate a loop. One condition is the loop count in the specified data register, and the other is the condition specified by the test. Note that DBcc  Dn,<label>  works only with 16-bit values in Dn. That is, loops greater than 65,536 cannot be implemented directly by this instruction. Two operations have to be carried out to implement a 32-bit operation.

REFERENCES

• A. Clements; The 68000’s Instruction Set, In: 68000 Family Assembly Language; pp.203-209; PWS Publishing Company; 1994.
• Dr. Mike Brady, Microprocessor Systems 1, dept of Computer Science, Trinity College Dublin: http://www.tcd.ie/Engineering/Courses/BAI/JS_Subjects/3D1/.
• Look on the Web at http://www.mee.tcd.ie/~assambc/3D1.

Source: http://www.mee.tcd.ie/~assambc/3d1_l09n.doc

Web site to visit: http://www.mee.tcd.ie

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#### 68000 Conditions Code Register

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##### 68000 Conditions Code Register

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